DESIGN OF AREA AND POWER EFFICIENT HALF ADDER USING TRANSMISSION GATE
نویسندگان
چکیده
منابع مشابه
Design of Area and Power Efficient Half Adder Using Transmission Gate
This paper gives an idea to reduce power and surface area of half adder circuit using very popular technique i.e. transmission gate. An adder is a digital circuit that performs addition of two numbers. In many computers and other kind of processors, adders are used not only in arithmetic logic unit but also in other parts of the processors where they are used to calculate addresses, table indic...
متن کاملDesign of Low Power and Area Efficient Full Adder using Modified Gate Diffusion Input
The low power techniques are becoming more important due to rapid development of portable digital applications; demand for high-speed and low power consumption.GDI (Gate Diffusion Input) is one of the low power and area efficient technique. GDI requires less number of transistors compared to CMOS technology. The basic cell of GDI consists of two transistors where three terminals i.e Gate, Sourc...
متن کاملDesign of Area and Power Efficient Modified Carry Select Adder
Adders are one of the widely used digital components in digital integrated circuit design. The Carry Select Adder (CSA) provides a good compromise between cost and performance in carry propagation adder design. However, conventional CSA is still area-consuming due to the dual ripple carry adder (RCA) structure. In this paper, modification is done at gate-level to reduce area and power consumpti...
متن کاملEfficient Layout Design of 4-Bit Full Adder using Transmission Gate
In any digital circuit surface area and power both are very important parameters. In this paper 4bit full adder using transmission gate is designed. To design 4bit full adder two methods are used. First is semi custom design method and second is full custom design method. In first semi custom design method a layout of 4-bit full adder is designed with available width and length of the transisto...
متن کاملHard ware implementation of area and power efficient Carry Select Adder using reconfigurable adder structures
In data processing processors, adder is a basic digital circuit. To perform any arithmetic operation, addition is the basic operation to perform. To compute fast arithmetic operations adder must be fastest. CSLA is the fastest adder when compare to RCA and CLA. From the structure of CSLA it is observed that there is a scope to reduce area further so that power can be lowered [3-4]. This paper p...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Research in Engineering and Technology
سال: 2015
ISSN: 2321-7308,2319-1163
DOI: 10.15623/ijret.2015.0404021